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LT3746
OPERATION
LED bus voltage V OUT will force a higher LED pin voltage
across the current sink, thereby dissipating more power
inside the part. See more details about the choice of the
LED bus voltage and the power dissipation calculation in
the Application Information section.
Dot Correction and Grayscale Digital-to-Analog
Conversion
The resistor on the I SET pin programs the nominal LED
current (4mA to 20mA) for all the channels. Individual LED
channel can be adjusted to a different current setting by
its own 6-bit dot correction register. The adjustable LED
current ranges from 0.5X to 1.5X of the nominal LED
current in 63 linear steps. See more details about setting
nominal LED current and dot correction in the Applications
Information section.
In addition to the dot correction current adjustment,
individual LED channels can also be modulated by their
own grayscale PWM dimming signal. To achieve a better
performance, all the grayscale PWM dimming signals
are synchronized to the same frequency with no phase
shift between rising edges. Each constant current sink is
enabled or disabled when its grayscale PWM dimming
signal goes high or low. This periodic grayscale PWM
dimming signal is generated by its own 12-bit grayscale
register with a duty cycle from 0/4096 to 4095/4096 and
a period equal to 4096 PWMCK clock cycles.
The generation of the grayscale PWM dimming signal
is best understood by referring to Figure 4. After EN = 1
is set, the first rising edge of the PWMCK signal will in-
crease the internal 12-bit grayscale counter from zero to
one and turn on all the LED channels with grayscale value
not zero. Each following rising edge of the PWMCK signal
increases the grayscale counter by one. Any LED channel
will be turned off when its 12-bit grayscale register value
is equal to the value in the grayscale counter. To generate
a 100% duty cycle for all the grayscale PWM dimming
signals, the PWMCK signal can be paused before counting
to the value in any individual 12-bit grayscale registers.
Setting EN = 0 will reset the grayscale counter to zero and
turn off all the LED channels immediately.
Dual-Loop Analog OR Control
The switching frequency can be programmed from 200kHz
to 1MHz with the resistor connected to the RT pin and it
can be synchronized to an external clock using the SYNC
pin. Each switching cycle starts with the gate driver
turning on the external P-channel MOSFET M1 and the
inductor current is sampled through the sense resistor R S
between the ISP and ISN pins. This current is amplified
and added to a slope compensation ramp signal, and the
resulting sum is fed into the positive terminal of the PWM
comparator. When this voltage exceeds the level at the
negative terminal of the PWM comparator, the gate driver
turns off M1. The level at the negative terminal of the PWM
comparator is set by either of two error amplifiers G M1
and G M2 . In this dual-loop analog OR control, the FB loop
G M1 regulates the FB pin voltage to 1.205V and the LED
loop G M2 regulates the minimum active LED pin voltage
(LED00 to LED31) to 0.5V. In the startup phase, the G M2
is disabled and the output LED bus voltage is regulated
towards the feedback resistor programmed LED bus volt-
age. This FB programmed voltage defines the maximum
LED bus voltage and should be programmed high enough
to supply the worst case LED string across temperature,
current, and manufacturing variation.
Adaptive-Tracking-Plus-Precharging
Higher system efficiency and faster transient response
are two highly anticipated specifications in an indi-
vidually-modulated multi-channel LED driver chip.
The LT3746 uses a patent pending adaptive-tracking-
plus-precharging technique to achieve both of them
simultaneously.
Besides 32 internal grayscale PWM dimming signals,
the part also generates another internal precharging
signal PRECHG. As shown in Figure 4, the PRECHG
signal divides any grayscale PWM dimming cycle
into two phases: tracking phase when PRECHG = 0
and precharging phase when PRECHG = 1. During
each grayscale PWM dimming cycle – 4096 PWMCK
clock cycles, the PRECHG signal stays low for the first
3584 clock cycles (7/8 of the grayscale PWM dimming
For more information www.linear.com/3746
3746fa
17
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